1. Field of the Invention
This invention pertains to a power saving 3-state circuit for use in integrated circuits. More particularly, the invention pertains to a BiCMOS power-up circuit that disables itself and draws no through current once operating voltage for the integrated circuit is achieved.
2. Description of Prior Art
In integrated circuits (IC's) having 3-state outputs, ON, OFF and electrically disabled, it is desirable to have the circuit output in the disabled mode during the time when the IC is powering up, typically between 0 volts and 3.5 volts, to attain the applied supply voltage (Vcc). This prevents the circuits from attempting to place a logic high or low signal on a bus while the supply voltage Vcc is ramping up from 0 volts. Such a condition is found in systems where a card containing 3-state circuits, attached to a bus, is powered down separately from the remainder of the system in order to conserve system power.
Although power-up 3-state circuits have been implemented in bipolar circuits, such circuits use signals opposite in phase for BiCMOS needs and continue to draw current after supply voltage has ramped up to Vcc. In BiCMOS circuits, where the total circuit current, Icc, in the disabled state may be only a few milliamps, the current used by the power-up 3-state circuit after the operating level of Vcc is reached may be a significant percentage of the total current and cause undesirable power-consumption by the IC circuit. The present invention avoids these limitations of prior art circuits by providing a BiCMOS power-up in 3-state circuit which generates signals having the correct phase for BiCMOS applications and which disables itself once the operating level of the supply voltage Vcc is achieved, thus drawing no Icc current.